my thoughts about VLSI/ASIC/Life/God…

I am trying for job but i am tired, my strategy is not working, i am not able to find job.

lets try to analyze what could have been done better.

• First and foremost though you have done Great things, it has to be documented well : RESUME , this is the first and foremost thing i would say which speaks for you, and if it does not get short-listed then doesnt make sense what knowledge base you have and who you are .
• Now lets see how to get the resume short-listed: who short-lists the resume? Its HR(human resources Department ) in most of the cases in many companies, what do they look for in the resume  [ Where he/she has done the education, which university, Which year, what stream, How many years of Experience, How much of that experience is relevant to the requirement, What company he is coming from, Does his previous company is also our kind of work they do, and some technical jargons/keywords/protocols/tool-names/skill-sets, papers, patents, Awards, (if any , as an added advantage). So Please Ensure whether these are there in your resume.
• O.k. now your resume is in the HR hands, now what next , HR passes your resume to the Technical manager of a specific Team, now it needs to get shortlisted for the requirement and need to be short-listed for the interview. so what does the Technical person looks for , he/she also looks the same in the previous para, as well as looks for projects, what kind of projects, how importance/relevance to our requirement, whether the projects looks meaningful or looks to be cooked up or junk  or Is the project just looks like an basic college ( i would call pre-undergrad stuff), what was the persons Roles and Responsibilities, how much was the duration of the project, what would had been the complexity level, and so many information any person would try to extract from it.
• Assume your resume gets short-listed , now what next : How to get through is the toughest of all questions to be answered, lets try to analyze…
• There are many aspects to the interview : Technical / Non-Technical stuff, what is the Technical Stuff ( Have you really done what ever you had written down in your Resume or false one, If you commit you have done something how confident are you in your answers, your analytical skills, Technical skills, If you have not ventured in to some domain and the interviewer asks some question then how do you really handle that stuff to try to get to options of solutions/trade-off’s, your strategy/methodology in solving the stuff and things like that.
• Now lets come to the Non-Technical skills : like Stress Management ( any real project will demand your time and increase your stress , so a basic stress test to check whether you will crip when project pressure comes or just an understanding how would you handle it, Time-Management: Fundamental point if you come to the interview late this is a data-point that you are messing up in the first and foremost , so plan yourself to be prompt to the interview schedule.
• Some Interviewers would be really boring you and testing your patience level, but still increase your threshold of patience level, it is just in that seat so be it, your turn would also come some time (Every Dog has its day , this is what my friend used to tell me, when i used to get pissed off with my interviews (10 years old story)…. so never loose patience.
• Now a days many companies has the fashion that more number of interviewers in an interview schedule for a candidate there is a wrong notion that the candidate feels the competition in getting that post/requirement filled, so never mind if five interviewers are interviewing view in a day , no wonder almost all the persons will start with "Tell me about your self" or "A brief about you" or "Sorry i was busy with the project , so i was not able to go-through your resume so please tell about you". So mentally prepare yourself as a tape-recorder to repeat the same question , the worst part would be you never know who is the deciding authority, so maintain your charm/rhythm/patience and above enjoy your day. So prepare for the basic questions like "Tell about yourself, very well, "What is the reason for leaving the company", "Prepare a brief about your project work/abstract of your project/complexities handled/any  good solution you had given in the tough time of the project, these things we usually work and forget as soon as the project ends, we as a Designer/Engineer lack a lot in document (say project documentation or be it a personal documentation (Resume writing)), so prepare yourself.
• "Attitude is the Key to Altitude"

To prepare yourself for the Technical Stuff, visit

http://www.vlsichipdesign.com/knowledgehome.html

Regarding Frequently asked interview Questions, almost 50 pages,  visit

http://www.vlsichipdesign.com/asic_vlsi_faq/faq_page1.html

Regarding the companies where to apply , visit (still many companies need to added, give me time)

http://www.vlsichipdesign.com/asiccompaniesinindia_page1.html

Search for chipdesign related jobs:

http://vlsichipdesign.jobamatic.com/a/jobs/find-jobs/q-ASIC+design

 I spend lot of my nights to write articles,my experiences, my lessons learnt, FAQ’s ( if you get a job I would be very very happy, i know the pain of getting job, and getting information is also tough, hardly people share.

lets share our knowledge, and make "World a Better Place to Live"

If you like it share it to your friends,

http://www.vlsichipdesign.com/tellafriend

My prayers & My Best Wishes

Share your Personal Interview Experiences in the Comment column please, it would be really helpful to others so that they dont make the same mistakes and loose an oppurtunity : so please comment( a small thing we could give to others, without costing us, i know you will do it)

Note : portion of the revenue from the advertisements are targetted towards charity.

·                     what is the scan methodology to be used/proposed

·                     Do i need to use a multiplexed flip-flop scan style or some other type

·                     should I need to have full-scan or partial scan

·                     how to stitch the boundary scan

·                     Should i use EDT or not?

·                     If I use EDT what should be my compression ratio

·                     how many test-clocks i should have

·                     What is the pin muxing of the test-clocks in the pads

·                     can i mux the test clocks with the functional clocks

·                     Should i need to perform at-speed testing or not

·                     what is the BIST strategy i should use to test memories

·                     how many number of test modes i should have in the chip

·                     what is the test strategy to test the pad logic

·                     what is the test mechanism to test PLL’s and analog block

·                     should I use logic-bist (L-BIST)

·                     What is the maximum length of the scan-chain

·                     what  is the tester to be used to test the chip

·                     what is the testing time

·                     what is the strategy i use for IDDQ test

·                     How do i by-pass the PLL’s

·                     what is the power-constraint when my chip is in the scan-mode

·                     In case of multi-voltage island designs what should be my test-strategy

·                     What is the scan-stitching strategy, is it from the module level scan-stitching, then i manually integrate it in the chip-level or i stitch the scan in the chiplevel .

·                     should i use test-models and stitch scan

·                     should negative flip-flops(if present in the design ) be part of the scan-chain

·                     If negative flip-flops, are present how do i propose a methodology to be a part-of the scan-chain

·                     what are steps i perform up-front in the design phase , so that the test-pattern’s are not more and takes more tester time

·                     what is the strategy  for clock-muxes

·                     Measures to ensure that there is no combinational feedback loops up-front in the design process, so that they are hard to be placed in a known-state

·                     what will be the reset strategy for the chip

·                     what is the allowable combinational depth so that the test-pattern count can be reduced.

·                     how to handle scan-enable versus test-modes so that higher fault coverage is achievable

To understand the concepts of the chip design,

http://www.vlsichipdesign.com

In my ten years of work experience i noticed one thing that we need to be very supportive to our colleagues be it personal or professional.

When there is a requirement where in you can add some value ,be a part of the solution to the problem, be it. When time comes and you were in need , at least you can count on someone. I too agree never expect something for what ever we do!!!

Almost we spend minimum of 33% of our daily time in our office, why not we make it so lively, if you love your workplace you can enjoy working , if so you can contribute better , at the end of the day as well if you back-trace the life you would be proud living.

I would share  with you all a picture which i got from my colleague[Thanks Manjul]

lets understand what is Yield and what is Reliability

yield is kind of a probability of failure say a processed device, whereas Reliability is a probability of failure over the period of time, initially while we were testing the device is functioning fine or good, over the period of time, it has failed .

what all could be reasons for it not being reliable ?

NBTI [negative bias temperature inversion]

courtesy : Cadence

Due to electric field stress and temperature, the hydrogen gets detached from Si dangling bond, creating interface traps. This problem is mainly noticed in PMOS transistors.

TDDB [ Time dependent Dielectric Breakdown] : some defects which are random, form a path from gate to channel through gateoxide.

Image courtesy : purdue Univ

HCI [Hot carrier injection] : The electrical field around the drain, generates injection of hot-carriers into SiO2 gate oxide layer. These carriers causes changes the charge distribution in the oxide-interface area.

courtesy : Cadence

picture courtesy : Sciencedirect/Elsevier

References:

1. Reliability Simulation in integrated Circuit Design , Cadence whitepaper

2. lecture notes by Ninad Pimparkar, Microelectronics Reliability phenomena

3. A comprehensive model of PMOS NBTI degradation by M.A. Alam, S. Mahapatra

 For Reading of Chip Design Articles,

http://www.vlsichipdesign.com

AIM : To reduce the EDA cost , what i will  look for? let me start listing down

• Let me list down the projects, respective project owners, Geographical location
• List down the tools, version, EDA vendor, number of licenses
• work with the EDA vendor to check the cost say based on usage or fixed for fortnight model, which suits my projects
• Mechanism to monitoring user information, geo graphical location, tools, usage time.
• Setting up a maximum number of license a user can have at a time
• set some trigger mechanism to send automatic mails, to know in case of any user exceeds limit of licenses
• in case of using many point-tools at different stages of chip development, work with a model from the EDA to consolidate say vendor consolidation, to get discounts.
• set up a team to perform tool-benchmarking to work with the design’s and aid suggestions whether the tool meets their specification
• check up setups or variables to be used , so that in case of any license hang-ups, then takes immediate actions to kill the job or suspend and resume kind of stuff.
• Work with the EDA tool vendor in case of any tool-bug and ensure that the next version of the tool comes with a production worthy.

For further reading related to chip design articles

http://www.vlsichipdesign.com

what do you see in the image is the types of bricks. Similar so in the chip  designing we do have lot of library cells to suite different implementation requirement.

some of the Types of library cells include:

• Boolen cells (Nand/Nor/Inverter, buffers,flip-flops,and, or…)
• Cells with different drive strengths for the same boolean cells like and_2, and_4 here _2 and _4 refers to the driving strength, this is one type of notation
• complex cells combining multiple functionalities like (And or/MUX, Mux invert, or invert)
• special cells like (filler cells, well tap cells, de-coupling cap cells, Tie cells)
• special cells for clocks like (clockcells having same rise and fall transitions cells)
• special cells for ESD(electro static Discharge (antenna diode cells)
• special cells like tristate cells
• power optimized cells like (clock gating cells, SRPG cells, level-shifter cells)

For further studies of Chip designing articles

http://www.vlsichipdesign.com

The same HR who talked about Rention of his company employees last-week, is now talking about lay-off’s/pink slips and thinks like that…. how to digest this.

There is nothing in our hands we just move along with the tide… Either “Retention or Layoff”. We as an employee just are at the recieving end . And it is a materialistic Business World where only money has value, and we all are here to do business.

No body to be blamed, it the due course of time which sets things to be prioritized.

Bottom-line of any business is to keep the share holders happy, irrespective of the market scenario.

At the good times, when things are going so good, the management talks about  ”Hires/gives retention bonus to its Employees/grants Joining bonuses and things like that” versus at the tough times “lay-off’s/Head-count reduction/No recruitment/Requirement freeze/recession/pink slip/cost cutting”.

so no blame game here…

how to accept the fact and prepare for this.

• first and foremost stop your shopping , rather spending time just by shopping during weekends.
• have a financial plan, have a work-out how long can you stretch if there is a job-cut for you… do you know , we all have lot of financial commitments[home-loan/car-loan/personal loan/credit-card balance/monthly expenses] for every month, open an xls sheet, and plan right now.
• stop or post-pone your vacation plan till you are so comfortable on your financial status.
• think about your parallel money making concepts, like part-time job if possible and thinks like that, plan , at least ’sow these seeds in your mind’ which will guide you.
• Based on your “personal balance-sheet”, work out on the areas where you can undergo cost-cutting.

 Courtesy : Toshiba

The beauty of flash memories are that they are electrically erasable but the data does not always get erased as soon as the power is switched off.

Jobseekers: The STA mock interview part 4 is moved to the below mentioned link.

http://www.vlsichipdesign.com/sta_mock_interview_part4.html
Jobseekers: To know more about On-chip Variation

http://www.vlsichipdesign.com/ocv.html

earlier Interview sessions about STA:

Part I :

http://chipdesignart.wordpress.com/2007/12/28/static-timing-analysis-mock-interview/

Part II:

http://chipdesignart.wordpress.com/2008/01/02/static-timing-analysis-mock-interview-part-ii/

Part III:

http://chipdesignart.wordpress.com/2008/01/03/static-timing-analysis-mock-interview-part-3/

The interview is moved to …please visit the below mentioned link

http://www.vlsichipdesign.com/sta_mock_interview_part3.html
I : we will connect later, I need to catch up for a meeting.

Meanwhile, Job-seeker, if you want to brush up, open your book and read, dont waste your time, "Life is all about Timing Optimization & Optimal Utilization, similar is Chip design "

http://www.vlsichipdesign.com/static_timing_analysis.html

earlier Interview sessions about STA:

Part I :

http://chipdesignart.wordpress.com/2007/12/28/static-timing-analysis-mock-interview/

Part II:

http://chipdesignart.wordpress.com/2008/01/02/static-timing-analysis-mock-interview-part-ii/