Serious about getting a job, VLSI FAQ on your way

what is the difference between mealy and moore state-machines

How to solve setup & Hold violations in the design

What is antenna Violation & ways to prevent it

We have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage?

what is tie-high and tie-low cells and where it is used

what is the difference between latches and flip-flops based designs

What is High-Vt and Low-Vt cells.

What is LEF mean?

what is DEF mean?

Steps involved in designing an optimal padring

What is metastability and steps to prevent it.

what is local-skew, global-skew,useful-skew mean?

What are the various timing-paths which i should take care in my STA runs?

What are the various components of Leakage-power?

What are the various yield-losses in the design?

what is meant by virtual clock definition and why do i need it?

What are the various Variations which impacts timing of the design?

What are the various Design constraints used while performing Synthesis for a design?

Specify few verilog constructs which are not supported by the synthesis tool.

Vds-Ids curve for an MOSFET, with increasing Vgs.

Basic Operation of an MOSFET.

What is Channel length Modulation?

what is body effect?

What is latchup in CMOS design and ways to prevent it?

What are the various design changes you do to meet design power targets?

what is meant by Library Characterizing:And many more questions and with answers…

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