Chip design is a very complex integration Process, where in we cannot afford to master in every part of the chip designing process why? : Time constraint.
so we do work with lot of 3 rd party I.P.[Intellectual property].
while some one delivers us an I.P. what all to look for? just a few thoughts/experiences shared dear designers.
- have you been delivered with the electrical specification and is the I.P. timing characteristics in-lined with the standard/protocol timing requirement, if an I.P. deals with specific standards.
- Does the I.P. comes with enough documentation like, Clock Flow Graph, Data flow Graph, integration guidelines, Clock tree guidelines (like insertion/skew), Timing guidelines,Integration guidelines, DFT guidelines….
Detailed information can be located at
http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/asic-knowledge-house.html
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