gate level simulation Mock-Interview

This is just a mock interview :

An Verification engineer claiming mastery in Gate-level simulation is coming for an Interview.

Interviewer: Welcome

Job Seeker: thanks

(aliasing I for Interviewer and J for Job-seeker)

I : In your resume you had mentioned that are an expert in GLS(Gate-level simulation), how comfortable are you.

J: Good comfortable.

I : one basic question, what is GLS.

J: GLS is a step in the Design flow to ensure that the design meets the functionality after placement and routing.

I: what all inputs are needed to perform GLS.

J: we Need post-routed netlist, Testbench, SDF (standard delay format file).

I: what is SDF? and how do you get this.

J: SDF is meant for Standard Delay format which will have all the delay information for the cell and the wire.

To generate SDF: we read in the routed netlist and the Extracted parasitics file(from Extraction Tool say StarRC extraction from Synopsys Inc, SPEF [ Standard Parasitics Extraction Format]).

I : Good.

I: Have you come across the term Formal Verification.

J: Yes

I : I have a doubt, say if I perform Formal Verification say Logical Equivalence across Gatelevel netlists(Synthesis and post routed netlist). Do you still see a reason behind GLS.

J: I like your approach, If we have verified the Synthesized netlist functionality is correct when compared to RTL and when we compare the Synthesized netlist versus Post route netlist logical Equivalence then i think we may not require GLS after P & R. But how do we ensure on Timing sir. To my knowledge Formal Verification Logical Equivalence Check does not perform Timing checks and dont ensure that the design will work on the operating frequency , so still i would go for GLS after post route database.

I : I partially agree, say i perform Static Timing Analysis, after post route , I take the post routed netlist and the extracted parasitics file and the Design timing constraints and perform the Design timing checks say all possible checks(setup/hold/clockgating/…) do you still see a reason for GLS after post route.

J: I dont know much about STA, but what ever i know, i will comment on it sir.

Yeah i agree with you but partially, i agree STA will check all the possible cases and corners and place the chip in different modes and things like that. But still see that GLS is a super-set over STA sir.

I : why do you think so.

J: Sir, if by mistake the designer has placed timing exceptions like false-paths,multi-cycle paths, then how we ensure that the design will meet timing requirements sir, so i feel ,that there should be some mechanism to validate as a counter check, so i still feel GLS is needed after post route design sir.

One more point sir, if the design is not synchronous friendly and purely asynchronous design then our STA will not favour us much.

I still feel one more reason for GLS is how to ensure that the design will be out of reset and our reset sequences and initialization sequences, boot-ups are fine.

So sire, i feel GLS is mandatory though it has limitations of Ensuring the quality of test vectors, Ensuring that the vectors will cover the complete area of the design (what i mean is the coverage analysis) and simulation run-time and things like that GLS ensure that the “Guarantee for Design Meeting for Functionality“

Interviewer: Good. You are appointed!!!

Note: To know the chip design concepts, worth visiting:

http://www.vlsichipdesign.com