clock tree synthesis constraints : Layout Requirement Specification

what all need to be communicated to the person who builds the clock tree’s. He need to aware of the complete information otherwise we will see surprises on timing after clock-tree synthesis has happenned or timing convergence will take a lot of time.

• first and foremost Clock-flow Graph , traversing of clocks to the complete Chip.
• List of all the clocks,Generated Clocks with frequencies.
• Clocks with number of sinks, This is just an extra input for the CTS designer to know the amount of sink and just to have a feel what could be the achieved insertion delay targets.
• …. Contd.

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http://www.vlsichipdesign.com/clock_tree_constraints.html