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	<title>Comments on: study about spare-cells</title>
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	<link>http://chipdesignart.wordpress.com/2007/12/20/study-about-spare-cells/</link>
	<description>vlsi,chip,silicon,jobs,Life,family,Personal,thoughts,ASIC,semiconductor,verification</description>
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		<title>By: Prathap</title>
		<link>http://chipdesignart.wordpress.com/2007/12/20/study-about-spare-cells/#comment-142</link>
		<dc:creator>Prathap</dc:creator>
		<pubDate>Tue, 29 Apr 2008 10:52:40 +0000</pubDate>
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		<description>Try to get the ist of cell in the design whose input and outputs ports are ties off as generally ports of floating cells are tied off due power issues.</description>
		<content:encoded><![CDATA[<p>Try to get the ist of cell in the design whose input and outputs ports are ties off as generally ports of floating cells are tied off due power issues.</p>
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		<title>By: Mujtaba Ahmed</title>
		<link>http://chipdesignart.wordpress.com/2007/12/20/study-about-spare-cells/#comment-112</link>
		<dc:creator>Mujtaba Ahmed</dc:creator>
		<pubDate>Sat, 01 Mar 2008 13:14:16 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignart.wordpress.com/2007/12/20/study-about-spare-cells/#comment-112</guid>
		<description>How do i know that there is a spare  cell in my netlist?</description>
		<content:encoded><![CDATA[<p>How do i know that there is a spare  cell in my netlist?</p>
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