experienced chip designers mistakes

i just thought to capture what all mistakes even an experienced designers used to make.

• check the version of your database in your views, there could be some check-out files.This is very frequent mistake, so better write a script to monitor and send mails every day what all are the checked out files specific to each views so that the specific designers could be aware of.
• While performing LVS checks, comparing the same spice deck in both the places.
• While performing formal verification logic equivalence checks comparing the same database for golden and revised netlist versions!!
• not validating the log files, whether things are fine and no warnings are present.
• Checking that the database is annotating properly after post route database and no annotation issues, because if you arenot aware of this information and started your timing analysis then you really dont know what you have qualified. This is very very important.
• Checking the check_timing or check_design [primetime/Design compiler] commands to know the design information and what the tool has understood after feeding the tool our relevant design constraints file. Similarly running check_model command [Magma] after place and route to know the design information.
• placing Spare-cells and in a well distributed fashion with all the possible flavours.
• forget to load with proper boot-code.

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