This is just a mock interview :
An Timing engineer claiming mastery in Static Timing Analysis is coming for an Interview.
The interview is available at
http://www.vlsichipdesign.com/sta_mock_interview.html
basics of Static Timing Analysis:
This is just a mock interview :
An Timing engineer claiming mastery in Static Timing Analysis is coming for an Interview.
The interview is available at
http://www.vlsichipdesign.com/sta_mock_interview.html
basics of Static Timing Analysis:
Categories: ASIC
Tagged: ASIC, chip, chip design, chip jobs, eda, silicon, vlsidesign, vlsijobs
5 responses so far ↓
BODDU // January 2, 2008 at 8:35 am |
Hi
Happy new year
i am new to STA(i am trying to learn)
could you please help me in getting the document on STA,at leat few concepts wise
Regards
BODDU Lokesh
Static Timing Analysis Mock Interview : Part 3 « my thoughts about VLSI/ASIC/Life/God… // January 3, 2008 at 11:34 am |
[...] http://chipdesignart.wordpress.com/2007/12/28/static-timing-analysis-mock-interview/ [...]
Static Timing Analysis Mock Interview : Part 4 « my thoughts about VLSI/ASIC/Life/God… // February 21, 2008 at 6:24 am |
[...] http://chipdesignart.wordpress.com/2007/12/28/static-timing-analysis-mock-interview/ [...]
Anirban // June 6, 2008 at 11:33 am |
This is wrong!
“Path 2: Path starting from register output and ending at the register output”
The path starts at the clock input of a flop and ends at the D input of the next flop stage. That’s why clock-to-Q delay is included in the path delay, and the next flop’s setup/hold checks will be applied at the D input.
james // June 8, 2008 at 6:00 pm |
I agree , Thanks for correcting…