my thoughts about VLSI/ASIC/Life/God…

Static Timing Analysis Mock Interview : Part 3

January 3, 2008 · 2 Comments

The interview is moved to …please visit the below mentioned link

http://www.vlsichipdesign.com/sta_mock_interview_part3.html
I : we will connect later, I need to catch up for a meeting.

Meanwhile, Job-seeker, if you want to brush up, open your book and read, dont waste your time, "Life is all about Timing Optimization & Optimal Utilization, similar is Chip design "

http://www.vlsichipdesign.com/static_timing_analysis.html

earlier Interview sessions about STA:

Part I :

http://chipdesignart.wordpress.com/2007/12/28/static-timing-analysis-mock-interview/

Part II:

http://chipdesignart.wordpress.com/2008/01/02/static-timing-analysis-mock-interview-part-ii/  

Categories: ASIC
Tagged: , , , , , , , ,

2 responses so far ↓

Leave a Comment