VLSI interview questions answered

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what is the difference between mealy and moore state-machines
how to solve setup and hold violations in the design
what is antenna violation & ways to prevent it
we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
what is tie-high and tie-low cells and where it is used
what is the difference between latches and flip-flops based designs
what is High-Vt and Low Vt cells
what is LEF mean?
what is DEF mean?
steps involved in designing an optimal padring
what is metastability and steps to prevent it
what is local-skew, global skew and useful skew
what are the various timing-paths which i should take care in my STA runs?
what are the various components of leakage-power
what are the various yield losses in the design
what is meant by virtual clock definition and why do i need it
what are the various variations which impacts timing of the design
what are the various Design constraints used, while performing synthesis for a design
specify few verilog constructs which are not supported by the synthesis tool
what are the various capacitances with an MOSFET?
Vds-Ids curve for an MOSFET, with increasing Vgs
explain basic operation of an MOSFET
what is channel length modulation
what is body effect
what is latchup in CMOS design and ways to prevent it?

what are the various design changes you do to meet design power targets
what is meant by library characterization
what is meant by wireload model
what are the measures to be taken to design for optimized area
what all will you be thinking while performing floorplan
what are the measures in the design taken for meeting signal integrity targets
what are the measures taken in the Design achieving better yield
what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
what are the steps incorporated for Engineering Change order[ECO]
what are the steps performed to achieve Lithography friendly Design
what does synthesis mean?
what are the pre-requistes to perform synthesis
can you explain the synthesis flow
what are the various ways to reduce clock insertion delay in the design

what are the various functional verification methodologies
what does formal verification mean
how will you time the output path in STA
how will you time the input path in STA
what is false path mean in STA and in what scenarios falsepath can come
what does multicycle path mean in STA and in what scenarios MCP can come
what are source synchronous paths in STA
Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it
we have multiple instances in RTL, do you do anything special during synthesis stage
what do you call an event and when do you call an assertion