In today’s world DFT(Design for TEst) is an no-excuse and design teams struggle hard to cover all the portions of the failures caused due to manufacturing.
The science behind this is DFT, rather it goes with the article, how to design rtl, which is friendly to DFT.
What all we can think up-front to make sure that the turnaround time to perform scan-insertion is less and we dont see the warnings in our test-insertion tool and then go back to RTL to ensure that we have coded our logic and our constructs are friendly enough for execution.
Some of the DFT violations include,
Modelling Violations,
improperly driven tri-states violations,
Asynchronous signal active during scan violations
flop clock/set/reset input not controllable
…….
to know more about this and to know how to code rtl to make DFT friendly visit the detailed article @
