Is life a weighbalance?

The article title is “Is Life a Weighbalance” and that too the weighbalance is so smart enough to balance automatically…

What do i mean?

Is to gain some thing or expertise in some thing do i need to loose in an another area or i loose focus in other area and over a period of time i loose.

An Individual being successful in financial domain ,  most of the time looses focus either in family/relationship or in health.

on the contrary a person who is so focussed in health and family the proabability that he may not be shinning in financial or other domain is quiet obvious…

I do undergo enough pain to get my muscles toned (Gym)

I do undergo stress, mental tention, tired, to be successful in my career. There may be articles, books talking about stress management, work and fun and things like that , but all top business do undergo lot of stress..

The point here is you decide the pain for what you value the most .

God has structured so well about Life, HE has given ownership to each and everyone about their individual decisions, individual pains, what each one thinks to attain in their life/living say one want to venture in business, one want to excel in sports, one want to decide and dedicate his life to spirituality… we so called Virtual owners, but ultimately the Real Owner (God) decides what to put in the weigh balance to weigh for some it is nano-grams and for some one it is tons…

It is that moment of life what you are in to , could be right side or left side of the weighing machine, could be called success or could be called failure, could be  called pain or could be called gain.

what to look for to make dft friendly RTL

In today’s world DFT(Design for TEst) is an no-excuse and design teams struggle hard to cover all the portions of the failures caused due to manufacturing.

The science behind this is DFT, rather it goes with the article, how to design rtl, which is friendly to DFT.

What all we can think up-front to make sure that the turnaround time to perform scan-insertion is less and we dont see the warnings in our test-insertion tool and then go back to RTL to ensure that we have coded our logic and our constructs are friendly enough for execution.

Some of the DFT violations include,

Modelling Violations,

improperly driven tri-states violations,

Asynchronous signal active during scan violations

flop clock/set/reset input not controllable

…….

to know more about this and to know how to code rtl to make DFT friendly visit the detailed article @

http://www.vlsichipdesign.com

what do other look in you?

hi,

i often wonder why the hell others look only negatives what i have.

like, You could have managed your family better?

you should have thought about savings/brought in early financial security?

why are you getting bald early?

watch your tummy its growing?

so, what do they really want…

• Do they want to get hold of the communication, and to convey that they are better off?
• do they want to pull me down, why the hell they cannot see the good things i have and spread the positive energy
• why they want to pull me down.

so the bottom-line is “you know better rather best about you” so never get you down, just because other person want to pull you down, keep yourselves away of the negative energies around you, it will eat your brain and stop you moving forward and be successfule.

Be positive and spread positive energies around.

how to schedule my day after layoff?

hi,

i am totally pissed off…. everywhere there is negative energies, colleagues , friends, neighbours are getting laid-off…

how do i get busy, and what i do today, how do i spend my time?

Do i partition  a day to cry, get depressed , eat and sleep or i schedule in a different way…

Huge transition when my outlook calendar gets overlapped to no entry in my calendar… what next??

now lets  plan ..

• Let me do financial budgetting, let me remember and do my budgetting and create a chart what i can call as necessity and what i can partition in luxury. Luxury portion needs to be revisited either to remove it completely or postpone like vacation,party, buying costly dresses, cars …
• Is there any way i can generate some money.
• This duration you can opt to strengthen your skills to “Sharpen your Saw” , check whether you can improve on your skills could be technical skills, soft skills, work on the area which needs improvement, we didnot found time to strengthen us , now if time and money permits can think of that. Do some certification, short-courses, higher studies.
• Write blog/maintain web-site share your work-experiences, educate others , now we need to increase self-moral. “Sharing is an art”
• Work on your areas of improvement
• Spend time with your family ,  we all had a complaint that work-life balance was not possible earlier, now we can work on the family.
• Spend time with your pets, they are stress bursters, will reduce our stress .

Energize yourself , your family, your friends, your neighbours, create positive energy amoung you around you, get charged and move on…

how to write a resume

Is reserving spirituality to old-age a right decision

After reading lot of articles about Management and spirituality  i came with some thoughts in me.

Spirituality , contented , self-happy is totally opposite to Business, Business model.

If we want to experience and practice spirtuality at the initial part of your life , then you may loose interest in the worldly matters like Money,Marriage,children.

Society drives us, and puts road-map across us to fulfill, like are you graduated, did you get the job, are you married, do you have kids, is your kid started walking, is your kid started talking, did you join the  kid in the pre-school, school,college, marry…..

To fullfill is we need money,health,good relationship.

If Spirituality is teaching me good and to satisfy the above needs, then i follow at the start of my life, but if Spirituality is about in search of God, i would like to reserve it at the later part of my life.

VLSI interview questions answered

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what is the difference between mealy and moore state-machines
how to solve setup and hold violations in the design
what is antenna violation & ways to prevent it
we have multiple instances in RTL(Register Transfer Language), do you do anything special during synthesis stage
what is tie-high and tie-low cells and where it is used
what is the difference between latches and flip-flops based designs
what is High-Vt and Low Vt cells
what is LEF mean?
what is DEF mean?
steps involved in designing an optimal padring
what is metastability and steps to prevent it
what is local-skew, global skew and useful skew
what are the various timing-paths which i should take care in my STA runs?
what are the various components of leakage-power
what are the various yield losses in the design
what is meant by virtual clock definition and why do i need it
what are the various variations which impacts timing of the design
what are the various Design constraints used, while performing synthesis for a design
specify few verilog constructs which are not supported by the synthesis tool
what are the various capacitances with an MOSFET?
Vds-Ids curve for an MOSFET, with increasing Vgs
explain basic operation of an MOSFET
what is channel length modulation
what is body effect
what is latchup in CMOS design and ways to prevent it?

what are the various design changes you do to meet design power targets
what is meant by library characterization
what is meant by wireload model
what are the measures to be taken to design for optimized area
what all will you be thinking while performing floorplan
what are the measures in the design taken for meeting signal integrity targets
what are the measures taken in the Design achieving better yield
what are the measures or precautions to be taken in the design when the chip has both analog and digital portions.
what are the steps incorporated for Engineering Change order[ECO]
what are the steps performed to achieve Lithography friendly Design
what does synthesis mean?
what are the pre-requistes to perform synthesis
can you explain the synthesis flow
what are the various ways to reduce clock insertion delay in the design

what are the various functional verification methodologies
what does formal verification mean
how will you time the output path in STA
how will you time the input path in STA
what is false path mean in STA and in what scenarios falsepath can come
what does multicycle path mean in STA and in what scenarios MCP can come
what are source synchronous paths in STA
Assume there is a specific requirement to preserve the logic during synthesis , how will you achieve it
we have multiple instances in RTL, do you do anything special during synthesis stage
what do you call an event and when do you call an assertion

how to prepare clock tree specification?

hi,

At first point we need to know in design front what are the clocking or clock-balancing requirements, that will trigger me to write down the clock-tree specification.

let me start listing down…

• Balance across flops

 http://www.vlsichipdesign.com/clock_tree4.jpg

Balance across flops and macros

 http://www.vlsichipdesign.com/clock_tree2.jpg

• Balance across macros

 http://www.vlsichipdesign.com/clock_tree3.jpg

• Balance clock across flops with useful skew

 http://www.vlsichipdesign.com/clock_tree6.jpg

• Balance flops across clock sources

 http://www.vlsichipdesign.com/clock_tree7.jpg

• Balance across source synchronous flops

 http://www.vlsichipdesign.com/clock_tree8.jpg

• Balance flops across clocks (say scan clock and functional clock)

 http://www.vlsichipdesign.com/clock_tree9.jpg

• Balancing across non-unate xor path

 http://www.vlsichipdesign.com/clock_tree10.jpg

• Placing clock-tree after clockgating cells to save power

 http://www.vlsichipdesign.com/clock_tree5.jpg

• Methods to reduce on-chip variation, by accounting CRPR[Clock Reconvergence pessimism Removal]

 http://www.vlsichipdesign.com/clock_tree1.jpg

For all your chip design requirements please visit

http://www.vlsichipdesign.com

Chip Design made Easy

VLSI project Ideas

hi,

Some of the list of VLSI projects i could think off….

VLSI Project Idea’s

LPDC[ Low Density Parity Check Code ] Encoders LPDC[ Low Density Parity Check Code ] Decoders Fractional PLL Physical Random Function generation with soft Errors Parity Prediction in Adders On Chip Bus Protocols USB[Universal Serial Bus Protocol] On Chip Speed-Monitors On Chip Process Variation Monitors Process Variation [Channel Length Variation] Modeling Process Variation [Lens abberation] Modeling On Chip variation list and their contribution in deration Wafer level variation More Projects can be located @ http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/vlsi-project-ideas.html If you know more add in the comments column, will be surely benefitting students who are looking for project ideas…

what to learn from your kids?

• learn to laugh
• learn to cry at times it relaxes your soul
• learn to play different games
• learn to live for that moment your kid does not plan ten years down the line .
• concentrate what you do right now.
• if things are not in your way, cry for a moment and do some other one , keep going.
• love to wear new dress keep you self-charged : color therapy
• Eager to learn new things.
• leave the habit of what others will think about you.. if you notice carefully your kid does not have this habit at all… my kid was asking “now what will lion mummy be doing” , but tough part is you need to find the right listener!!!
• learn to share you get transformed so easily.
• reserve time to attend functions/celebrations/festival give your best forget above all worries , relaxes your soul.
• keep things simple, dont complicate, you can find out solution so easily.
• Studies and researches comments Experts complicates things and beginners find lot of options.
• live every moment.
• stop following pre-existing datapoints/history, may happen may not happen, kids most of the time dont know about any history so they may bring a new solution.
• learn Energy Management